An embodiment relates to a nonvolatile memory device and, more particularly, to a data input circuit configured to receive data at a double data rate (DDR) and a nonvolatile memory device including the same.
A nonvolatile memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and a plurality of cell strings corresponding to the respective bit lines.
Semiconductor devices, such as the above-described nonvolatile memory device, operate in response to a periodical clock. Here, a circuit has to be fabricated differently depending on when the circuit will operate while the clock is input. A flash memory device is typically configured to operate at the rising or falling edge of a clock.
FIG. 1A shows the data input apparatus of a nonvolatile memory device.
The nonvolatile memory device includes eight input/output (IO) pins configured to receive data as the unit of eight bits. Data IO means for receiving external input data EXT_IO<7:0> as internal data INT_IO<7:0> through the respective IO pins may be configured as in a data input unit 100 of FIG. 1A. The data input unit 100 may include a D flip-flop. The D flip-flop is configured to output data, received in response to a clock, without a change.
The data input unit 100 is configured to output data, input to an input terminal D in response to an input clock signal, to an output terminal Q. Here, the external input data EXT_IO<7:0> is input to the input terminal D, and the internal data INT_IO<7:0> is output from the output terminal Q. In the data input unit 100, an input control signal (write enable; WE#) functions as the clock signal.
An operational timing diagram of the data input unit 100 is described below.
FIG. 1B is a timing diagram showing an operation of FIG. 1A.
Referring to FIG. 1B, the external input data EXT_IO<7:0> is output as the internal data INT_IO<7:0> at the rising edge of the input control signal WE#.
The capacity of a nonvolatile memory device has continued to increase. With the increase in the memory capacity, the number of page buffers increases. For example, in a memory device having the memory capacity of 2 GB, the number of page buffers may be 2048. The number of page buffers of a memory device having the memory capacity of 8 GB may be 4096. Further, in a memory device having the memory capacity of 16 GB, the number of page buffers may be 8192 or more.
If the number of page buffers proportionally increases with an increase in the memory capacity, when external data is received for a program operation, the time that it takes to load the data on all the page buffers increases. The program time is greatly increased with the increase in the data loading time. It has a significant influence on the performance of a nonvolatile memory device.
Furthermore, the data loading time is becoming an important issue because mobile devices being developed are required to process high-capacity data at high speed.